1. Field of the Invention
The present invention relates to an automatic floorplan operation apparatus for design automation of a semiconductor integrated circuit such as a standard cell and a gate array and more particularly, to an automatic floorplan operation apparatus for performing a layout of cells in a plurality of arrangeable areas which are permitted to be overlapped.
2. Description of the Prior Art
A design procedure of a semiconductor integrated circuit (called LSI hereinafter) is ordinarily carried out as shown in FIG. 1. Namely, a system design is carried out in a step S1, then a logic design to compose an electronic circuit is prepared in a step S2. Subsequently, a layout design on an LSI chip based on the logic design step S2 is carried out in a step S3, further the layout design is verified in a step S4. Thereafter, a sample is prepared in a step S5.
A floorplan is made before an automatic placement and a wiring process in the layout design step S3. For example, the floorplan is prepared to obtain a suitable layout on a semiconductor chip, by which various circuit elements can be uniformly arranged. Moreover, the plan also is made for shortening wiring length to control delay of signals under severs timing conditions and for reducing the whole area of the chip.
FIG. 2 shows an example of a layout of an LSI. In the floorplan, an outline of the composition of a chip 2 is determined. Namely, the object of the floorplan is to determine how to wire a power source wire 1 to the respective cells 3 in the chip 2, what order input-output cells 4 are arranged on the periphery of the chip 2, where blocks 5, such as a RAM and a ROM, having relatively large areas and previously completely designed are to be arranged on the chip 2, and where collective cells respectively having specific functions are arranged.
Particularly, the result of the floorplan process concerning shape and layout region of the collective cells is very important because it has a great deal of influence on layout and wiring after the floorplan, the integration degree of elements in the chip, and efficiency in the use of the chip area and the design.
FIGS. 3A to 3D show examples of results of floorplans for an LSI in which respective elements are related in a logical hierarchy structure.
Reference characters A, B, C and "others", respectively designate modules in which the collective cells and macro blocks are divided. Namely, FIGS. 3A to 3D show several ways to separately arrange these modules A, B, C, D and others on the chip 2. For example, in the logical hierarchy structure shown in FIG. 3A, when only the module C has severe conditions on timing, a floorplan is based particularly on the position and the shape of the module C, while the result of a floorplan based on the building block method becomes as shown in FIG. 3B, and that based on the slicing structure method becomes as shown in FIG. 3C.
However, in the case of the building block method, an unavailable area 6 (wiring area among blocks) where cells can not be arranged is made around the modules or blocks A, B, C, D, and others. When an unavailable area 6 is defined in advance, the flexibility of automatic placement and wiring after the floorplan is restricted, so that the placement and wiring can not be carried out effectively.
In the case of the slicing structure method, the unavailable area is not made around the blocks A, B, C, D and others. However, since overlaps between these blocks are not permitted, an extremely long longitudinal or transverse area 7 as shown in FIG. 4A is likely to be required. When an arrangeable area is extremely long and thin, the automatic placement and wiring can not be carried out effectively. Thus, the block area must be enlarged more than necessary.
To solve the problems, it is possible to use a method in which arrangeable areas are permitted to be overlapped as shown in FIGS. 3D and 4B. As compared to the former two methods in which all the collective cells are assigned to each area even if there is no necessity for constraints such as timing constraints, the shapes and the positions of the respective collective cells can be optionally decided by the latter method where the arrangeable areas are permitted to be overlapped. Thus, automatic layout and wiring are not restricted so severely as in the former methods, thereby expecting a higher density layout. For a layout designer, the working amount can be reduced by flexibility of design owing to the method in which arrangeable areas are permitted to be overlapped by optionally determining the shape and the position of the areas.
For example, in the case of the building block method shown in FIG. 3B, the wiring area must be considered to decide the positions of the respective blocks A, B, C, D and others. While, in the case of the slicing structure method shown in FIG. 3C, the positioning for the modules A, B, D, and others other than the module C which is not particularly required must be decided. Therefore, the flexibility of design is restricted. While, in the case of the method shown in FIG. 3D, where the arrangeable areas are permitted to be overlapped, only the required positioning of the module C can be preferentially decided, then the automatic layout of the modules can be decided suitably and flexibly.
Moreover, as compared to the methods where the shapes and positions of these modules are decided without overlaps of the arrangeable areas, it is possible for the designer to approximately decide them. For example, in the layouts of the floorplan shown in FIGS. 3B and 3C, the designer must evaluate the shapes and the positions of the respective modules relatively correctively in advance to reduce the unavailable area. Therefore, the flexibility of design is restricted. When rough evaluation can be acceptable in the case of method where the arrangeable areas are permitted to be overlapped, flexibility is increased.
FIG. 5 shows another example of a floorplan in which overlap is also permitted. In a chip 2 having the same logical-hierarchy structure as shown in FIG. 3A, cells .alpha. (other than cell groups of a1, a2 composed of collective cells in a module A) are with overlap assigned on arrangeable areas (herein, the whole area in the chip 2) of cells and macro blocks other than modules A, B in the chip 2. Moreover, arrangeable areas .beta. for cells and macro blocks in the module B, .alpha.1 for cells in the cell module a1, and .alpha.2 for the cell module a2 in the module A are respectively so arranged as to be slightly overlapped with one another. When such a floorplan in which overlap permitted is used, the unavailable area as mentioned above is not fixed on the chip 2, further the shapes and the positions of the respective modules for the cells and blocks are not restricted. Thus, the floorplan should have a wide flexibility of design.
However, in the methods where the overlap is permitted, the overlap can not be permitted without limit. To utilize the chip area efficiently, it is necessary to eliminate non-uniformity of cell density in the chip in which a ratio is a ratio of the cell area to the area of the chip substrate, and to make a floorplan to realize a facile layout and wiring for the post-processes.
The reasons are as follows. In a portion where the cell density is high, the density of wiring becomes extremely high. As a result, unwired portions or wiring shorts between the wires are likely to be caused in the case of an LSI of the gate array type, or the chip area must be increased in an LSI of the standard-cell type. While, in a portion of lower cell density, of course, unused portions are generated in the placement and the wiring area. Namely, when the cell density is non-uniform, a portion of an excessively high density and another portion having unused area are present in the chip at the same time, thus the chip area is not effectively used. Therefore, it is important to make the cell density uniform in the floorplan in which the overlap of arrangeable areas is permitted.
Various methods to automate a floorplan based on the building block method and the slicing structure method have been conventionally proposed. Particularly in the method called the Force Directed Method (FDM; based on a dynamic technique) used in the building block method, a wiring length is defined by an evaluation value as a positional energy, and the optimization of the floorplan is carried out by minimizing the evaluation value by mutually shifting the respective arrangeable areas little by little (cf. reference literature 1, 2, and 3 hereinafter).
In the FDM, the algorithm is relatively easy, and a plan by a designer can be an initial value, further the designer can easily improve the arrangeable areas automatically designed. However, the inventors have not seen examples where the dynamic technique is applied to the automatic floorplan in which the overlap is permitted or to making cell density uniform.
As stated above, in the building block method and the slicing structure method used in the conventional floorplan, the flexibility of design for the arrangeable areas is relatively narrow. While, even in the conventional method in which the overlapped areas are permitted, making cell density uniform in a chip is not sufficiently realized.